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CPU Pipeline Simulator
Visualize a 5-stage CPU pipeline with data hazard detection, forwarding paths, branch prediction, and pipeline stalls. Step through clock cycles or auto-play.
Presets:
Parsed (0):
Registers:
R0
0
0
R1
1
1
R2
2
2
R3
3
3
R4
4
4
R5
5
5
R6
6
6
R7
7
7
Pipeline Diagram (Cycle 0):
CPI: --IPC: --Stalls: 0Flushes: 0
| Cycle | IF Fetch | ID Decode | EX Execute | MEM Memory | WB Write-Back |
|---|---|---|---|---|---|
| Click Step or Play to begin simulation | |||||
Stall (bubble)
RAW Hazard
Forwarding
Flush (branch)
Cycle: 0
Completed: 0
CPI: --
IPC: --
Toggle forwarding on/off to see how stalls change. Compare CPI with and without data forwarding. Branch prediction uses always-not-taken strategy with pipeline flush on misprediction. All simulation runs entirely in your browser.